Memory attribute sharing between differing cache levels of multilevel cache

摘要

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

主权项

1. A data processing system comprising:
a central processing unit executing program instructions to manipulate data; a first level data cache connected to said central processing unit temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; a first level data cache controller connected to said first level data cache controlling data transfers into and out of said first level data cache; a second level cache connected to said first level cache including second level cache temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; a second level data cache controller connected to said second level data cache controlling data transfers into and out of said second level data cache, said second level cache controller including a plurality of first memory attribute registers each storing a plurality of memory access attributes for a corresponding address range of external memory including cacheability bits; and wherein said first level data cache controller further includes a plurality of second memory attribute registers, each second memory attribute register storing a copy of said cacheability bits of a corresponding one of said plurality of first memory attribute registers for said corresponding address range of external memory.