Semiconductor device and method of manufacturing the same

摘要

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

主权项

1. A semiconductor device having a first MISFET and a second MISFET formed over a semiconductor substrate, the semiconductor device comprising:
(a) the first MISFET including
(a1) a first gate insulating film formed over the semiconductor substrate;(a2) a first gate electrode formed over the first gate insulating film; and(a3) a first semiconductor region formed in the semiconductor substrate, the first semiconductor region being located at one side of the first gate electrode; (b) the second MISFET including
(b1) a second gate insulating film formed over the semiconductor substrate, a thickness of the second gate insulating film being thicker than a thickness of the first gate insulating film;(b2) a second gate electrode formed over the second gate insulating film and formed of a first conductive film of a same layer as a layer of the first gate electrode; and(b3) a second semiconductor region and a third semiconductor region formed in the semiconductor substrate, the second semiconductor region and third semiconductor region being located at both sides of the second gate electrode respectively; (c) an insulating film formed over the first MISFET and the second MISFET; (d) a first plug formed in the insulating film and electrically connected to the first semiconductor region; (e) a second plug formed in the insulating film and electrically connected to the second semiconductor region; (f) a third plug formed in the insulating film and electrically connected to the third semiconductor region; (g) a first wiring layer formed over the insulating film and electrically connected to the first plug; (h) a second wiring layer formed over the insulating film and electrically connected to the second plug, the second wiring layer being formed of a second conductive film of a same layer as a layer of the first wiring layer; and (i) a third wiring layer formed over the insulating film and electrically connected to the third plug, the third wiring layer being formed of the second conductive film of the same layer as that of the first wiring layer and the second wiring layer, wherein the first gate electrode is overlapped with the first wiring layer in a plan view, wherein the second wiring layer is spaced away from the second gate electrode in the plan view, and wherein the third wiring layer is spaced away from the second gate electrode in the plan view.