Apparatuses and methods for compressing data received over multiple memory accesses

摘要

Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator configured to compare data provided by a group of memory cells associated with a repair address. Each subset of one or more bits of the data is sequentially provided by the group of memory cells responsive to a respective memory access of a plurality of memory accesses. The example compression circuit further including an error bit latch coupled to the comparison circuit. The error bit latch configured to, responsive to an output received from the comparison circuit indicating an error, compress the data to an error bit by setting the error bit to an error detected state and latching the error bit having the error detected state.

主权项

1. An apparatus, comprising:
an array of memory cells, wherein the array is divided into a plurality of groups of memory cells, a group of memory cells of the plurality of groups of memory cells being associated with a respective channel of a plurality of channels, the respective channel of the plurality of channels configured to provide data from the group of memory cells of the plurality of groups of memory cells responsive to a memory access; and a compression block coupled to the array of the plurality of memory cells, the compression block comprising a plurality of compression circuits, a compression circuit of the plurality of compression circuits coupled to the respective channel of the plurality of channels, wherein the compression circuit of the plurality of compression circuits is configured to compare first data provided by the respective group of memory cells of the plurality of groups of memory cells responsive to a first memory access with second data provided by the respective group of memory cells of the plurality of groups of memory cells responsive to a second memory access and, responsive to the comparison of the first data with the second data indicating an error, to set an error bit to an error detected state and to latch the error bit having the error detected state.