Method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers

摘要

A method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers allows for either decreased register spillage or decreased area and power consumption of a microprocessor. The microprocessor takes advantage of register bypass logic to write short-lived values to virtual registers, which are discarded instead of being written to the register bank, thus reducing register pressure by avoiding short-lived values being written to the register bank.

主权项

1. A method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers, the method comprises the steps of:
providing a microprocessor, wherein a periodic clock cycle coordinates commands executed by the microprocessor; providing a register bank, wherein the register bank comprises a number of physical registers (R); providing a specific pipeline datapath and a plurality of optional additional pipeline datapaths within the microprocessor, wherein N is the total number of pipeline datapaths; wherein the specific pipeline datapath and the plurality of optional additional pipeline datapaths each comprise a plurality of pipeline stages; wherein the plurality of pipeline stages includes an execution stage and a writeback stage; wherein the execution stage occurs before the writeback stage; wherein the specific pipeline datapath and the plurality of optional additional pipeline datapaths each comprise a number of pipeline registers (P) between the execution stage and the writeback stage; processing a source instruction with the specific pipeline datapath; processing a corresponding instruction with an arbitrary pipeline datapath, wherein the arbitrary pipeline datapath is either the specific pipeline datapath or one of the plurality of optional additional pipeline datapaths; sequentially executing the plurality of pipeline stages for both the specific pipeline datapath and the plurality of optional additional pipeline datapaths; producing an output value with the specific pipeline datapath; storing the output value within the register bank, if the output value is not used as an input value for the corresponding instruction within P clock cycles; storing the output value within the register bank, if the output value is used as an input value for the corresponding instruction within P clock cycles; and if the output value is used as a subsequent input value for a future arbitrary subsequent instruction, wherein the future arbitrary subsequent instruction uses the output value as a subsequent input value after P clock cycles; storing the output value within a Pipeline Virtual Register (PVR), if the output value is used as an input value for the corresponding instruction within P clock cycles, and if the output value is not used as an input value for any subsequent instructions.