发明名称 SWITCHING A COMPUTER SYSTEM FROM A HIGH PERFORMANCE MODE TO A LOW POWER MODE
摘要 A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.
申请公布号 US2015317269(A1) 申请公布日期 2015.11.05
申请号 US201514798079 申请日期 2015.07.13
申请人 ADVANCED MICRO DEVICES, INC. 发明人 Macri Joseph D.;Bouvier Daniel L.
分类号 G06F13/40;G06F1/32;G06F13/28 主分类号 G06F13/40
代理机构 代理人
主权项 1. A computer system, comprising: a common memory; a first processor connected to the common memory, the first processor including: one or more central processing unit (CPU) cores;a memory controller hub in communication with each of the CPU cores;one or more memory controllers in communication with the memory controller hub and the common memory;a bidirectional communication protocol controller in communication with the memory controller hub; anda memory bus connected to the common memory; a second processor in communication with the first processor, the second processor including: one or more CPU cores;a memory controller hub in communication with each of the CPU cores;one or more memory controllers in communication with the memory controller hub and the common memory;a bidirectional communication protocol controller in communication with the memory controller hub; anda memory bus connected to the common memory; and a polymorphous link between the first processor and the second processor, whereby the first processor may access the common memory through the polymorphous link.
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