| 摘要 |
PROBLEM TO BE SOLVED: To obtain a data transfer control device which reduces a circuit scale and a load applying to a CPU.SOLUTION: An input-output port 6 for an image processing module in a DMAC 1 includes an input part for inputting address information ADD 2 and an address specification request signal REQ 2 from an image processing module 2, and an output part for outputting a return signal VAL 2 for instructing effective reception of the address information ADD 2. The input-output port 6 for an image processing module can execute signal input-output control processing for responding to the address specification request signal REQ 2, and returning a return signal VAL 2 for instructing to confirm the effective reception of the address information ADD 2 during confirming the effective reception. A memory access control part 7 executes memory access processing for accessing an access target storage area of a memory 3 on the basis of address information ADD 1 (=ADD 2) received through the input-output port 6 for an image processing module. |
