SSL/GSL GATE OXIDE IN 3D VERTICAL CHANNEL NAND

摘要

A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips.

主权项

1. A memory device including an array of strings of memory cells, comprising:
a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips; a plurality of vertical active strips between the plurality of stacks; charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertical active strips; and gate dielectric, having a different composition than the charge storage structures, in interface regions at cross-points between the vertical active strips in the plurality of vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips.