COMPUTER ARCHITECTURE HAVING SELECTABLE, PARALLEL AND SERIAL COMMUNICATION CHANNELS BETWEEN PROCESSORS AND MEMORY

摘要

A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

主权项

1. An electronic computer comprising:
a processor system having:
(a) a first latency-sensitive processor executing a general instruction set for general purpose computation;(b) a second latency-insensitive processor executing a specialized instruction set for specialized computation, wherein the latency-insensitive processor is less sensitive to latency in access to electronic memory than the latency-sensitive processor; an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system; a parallel bus communicating between the processor system and the memory providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane; a serial bus communicating between the processor system and the memory providing transmission of different bits of given data words serially on at least one conductor of a serial lane; and a memory access manager preferentially routing memory access by the latency-sensitive processor through the parallel bus and memory access by the latency-insensitive processor through the serial bus.