发明名称 SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME
摘要 A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
申请公布号 US2015318244(A1) 申请公布日期 2015.11.05
申请号 US201514750665 申请日期 2015.06.25
申请人 TERA PROBE, INC. 发明人 Mizusawa Aiko;Okada Osamu;Wakabayashi Takeshi;Mihara Ichiro
分类号 H01L23/522;H01L23/532;H01L23/00;H01L23/528 主分类号 H01L23/522
代理机构 代理人
主权项 1. A semiconductor device comprising: a semiconductor substrate including an upper surface and a plurality of active semiconductor elements; a low dielectric film wiring line laminated structure portion which is provided on the upper surface of the semiconductor substrate, and which has a laminated structure including a plurality of low dielectric films and a plurality of wiring lines, each of the low dielectric films having a relative dielectric constant of 3.0 or lower, and at least one of said plurality of low dielectric films including a porous type film; a passivation film made of an inorganic material and formed on an upper surface of the low dielectric film wiring line laminated structure portion; and an organic resin layer including an upper portion which directly contacts with and covers an upper surface of the passivation film, and a side peripheral portion which directly contacts with and covers a side peripheral surface of the low dielectric film wiring line laminated structure portion, the organic resin layer protecting at least one of the low dielectric films of the low dielectric film wiring line laminated structure portion from peeling off from an under layer or the upper surface of semiconductor substrate, wherein the under layer is formed by another one of the low dielectric films, wherein the low dielectric films of the low dielectric film wiring line laminated structure portion, the passivation film, and the upper portion of the organic resin layer respectively include a plurality of through openings for an electric connection of the active semiconductor elements, and wherein a side peripheral surface of the passivation film is located inward from the side peripheral surface of the low dielectric film wiring line laminated structure portion.
地址 YOKOHAMA JP
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