发明名称 Method of forming a semiconductor device employing an optical planarization layer
摘要 A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.
申请公布号 US9177874(B2) 申请公布日期 2015.11.03
申请号 US201314012563 申请日期 2013.08.28
申请人 GLOBALFOUNDRIES Inc. 发明人 Patzer Joachim;Pakfar Ardechir;Thurmer Dominic;Wang Chih-Chun;Riviere Remi;Melzer Robert;Haussdoerfer Bastian;Weisheit Martin
分类号 H01L21/00;H01L21/66;H01L21/8238;H01L27/06;H01L21/311;H01L21/3105 主分类号 H01L21/00
代理机构 Amerson Law Firm, PLLC 代理人 Amerson Law Firm, PLLC
主权项 1. A method for the manufacture of a semiconductor device, the method comprising: providing a semiconductor substrate comprising a first active device area separated from a second active device area by a first isolation region formed in said semiconductor substrate, wherein said second active device area comprises a transistor in an intermediate processing stage, said transistor comprising a gate electrode; forming a sacrificial oxide layer over said first and second active device areas; forming an optical planarization layer (OPL) over said sacrificial oxide layer, said OPL covering at least said first and second active device areas; forming a patterned mask layer over said OPL, said patterned mask layer covering at least said first active device area and exposing at least a portion of said OPL formed above said second active device area; and etching said exposed portion of said OPL in the presence of said patterned mask layer to expose a portion of said sacrificial oxide layer formed over said gate electrode of said transistor.
地址 Grand Cayman KY