Memory with bit line capacitive loading

摘要

A memory that may allow for the detection of weak data storage cells may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.

主权项

1. An apparatus, comprising:
a plurality of columns;
wherein each of the columns includes a plurality of data storage cells, wherein each given one of the data storage cells is configured such that in response to assertion of a row selection signal, the given data storage cell generates a column output; and a column multiplexer coupled to receive input data from the plurality of columns, wherein the column multiplexer is configured to controllably select data from one of the plurality of columns to generate a column multiplexer output signal dependent upon a column selection signal; and a sense amplifier configured to amplify the column multiplexer output signal by the gain level of the sense amplifier in response to assertion of a control signal; and a load circuit configured to couple a load device to the input of the sense amplifier, wherein the load circuit is controllable to provide a first load or a second load dependent upon a load selection signal.