Dual-edge gated clock signal generator

摘要

A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.

主权项

1. A clock signal generator for generating a gated clock signal for use with dual-edge triggered circuits, the clock signal generator comprising:
a first detector that receives an input clock signal, a clock gating signal and a feedback of the gated clock signal for generating, when the clock gating signal is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that the input clock signal and the gated clock signal had when the clock gating signal transitioned from asserted to de-asserted; and a second detector that receives the input clock signal, the clock gating signal and the first detector output signal for generating, when the clock gating signal is de-asserted, as the value of the gated clock signal the value of the input clock signal or the complementary value of the input clock signal as a function of the first detector output signal, and for maintaining, while the clock gating signal is asserted, the value that the gated clock signal had when the clock gating signal transitioned from de-asserted to asserted, wherein the second detector selects as the value of the gated clock signal the value of the input clock signal if the first detector output signal is de-asserted, and the value of the complement of the input clock signal if the first detector output signal is asserted.