发明名称 Stacked semiconductor capacitor structure
摘要 The present invention discloses a capacitor in an integrated circuit which comprises a first and second conductive lines substantially parallel to each other and having a thickness equals substantially to a sum of a via thickness and an interconnect thickness, the first and second conductive lines, the via and the interconnect being formed by a single deposition step, and at least one dielectric material in a space horizontally across the first and second conductive lines, wherein the first and second conductive lines serve as two conductive plates of the capacitor, respectively, and the dielectric material serves as an insulator of the capacitor.
申请公布号 US9177908(B2) 申请公布日期 2015.11.03
申请号 US200711742421 申请日期 2007.04.30
申请人 Taiwan Semiconductor Manufacturing Company, Limited 发明人 Liaw Jhon Jhy
分类号 H01L29/92;H01L23/522;H01L23/532;H01L49/02 主分类号 H01L29/92
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A horizontal capacitor in an integrated circuit, comprising: a plurality of first conductive lines and second conductive lines formed on a first dielectric layer and placed in a cross-finger manner to form a first plate for serving as a cathode and a second plate for serving as an anode of the capacitor, wherein the first and second conductive lines are provided by filling first and second via recesses with a conductive material, thereby forming first via lines and second via lines that are extended in a horizontal direction to form the first and second plates placed in a cross-finger manner, said via lines being formed in a second dielectric layer disposed on the first dielectric layer; and a first connection area horizontally connected to the first plate and a second connection area horizontally connected to the second plate for connecting the first and second plates to other parts of the integrated circuit, respectively, wherein each of the first and second connection areas comprises a channel portion disposed on a via portion, the channel portion being formed by filling channel recesses and wider than the via portion, and both the channel and via portions being formed in the second dielectric layer and filled with said conductive material, and wherein a height of the first and second conductive lines is substantially equal to that of the connection area.
地址 Hsin-Chu TW