Multiple Rate Signature Test to Verify Integrated Circuit Identity

摘要

Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example.

主权项

1. A method for screening a plurality of integrated circuits (IC), the method comprising:
fetching a sequence of test vectors from a memory coupled to a tester; providing one or more bits from each test vector to the tester; forming a test pattern by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors; and applying the test pattern to an input pin and monitoring a resulting signal on an output pin of each one of the plurality of ICs.