Method for Improving E-Beam Lithography Gate Metal Profile for Enhanced Field Control

摘要

A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.

主权项

1. A method of forming a semiconductor device, comprising:
providing a substrate; forming a multi-layer dielectric stack on the substrate; patterning a multi-layer resist stack on the multi-layer dielectric stack to define a first etch opening over the multi-layer dielectric stack; etching the multi-layer dielectric stack with a plurality of different etch steps to form a stepped opening in the multi-layer dielectric stack which exposes a gate contact surface of the substrate; and forming a conductive gate electrode in contact with the gate contact surface of the substrate and in the stepped opening to form a contact base portion with one or more gate ledges, the conductive gate electrode comprising gate electrode sidewall extensions that are vertically spaced above the one or more gate ledges.