Computer Processor With Generation Renaming

摘要

A processor including a register file having a plurality of registers, and configured for out-of-order instruction execution, further includes a renamer unit that produces generation numbers that are associated with register file addresses to provide a renamed version of a register that is temporally offset from an existing version of that register rather than assigning a non-programmer-visible physical register as the renamed register. The processor includes a small reset DHL Gshare branch prediction unit coupled to an instruction cache and configured to provide speculative addresses to the instruction cache.

主权项

1. A processor, comprising:
a reservation queue; a renamer coupled to the reservation queue and configured to produce a generation number and to communicate the generation number to the reservation queue; a register coupled to the reservation queue and configured to store a value; an execution pipe coupled to the reservation queue; and a buffer coupled to the execution pipe and configured to receive an output of the execution pipe, and further coupled to the reservation queue and configured to communicate the output of the execution pipe to the reservation queue.