Solid state drive tester

摘要

Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

主权项

1. A solid state drive tester comprising:
a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory, wherein the test control unit includes: an embedded processor for generating the test pattern corresponding to the test condition input by the user; a vector memory for storing expectation data corresponding to the test pattern created by the embedded processor; and a fail processor for comparing expectation data stored in the vector memory with test result data acquired from the embedded processor to determine a fail state, and processing fail information generated upon failure, and wherein the fail processor includes: a comparator comparing the expectation data stored in the vector memory with the test result data acquired from the embedded processor and generating a fail signal when the expectation data differs from the test result data; a fail counter counting the number of fail signals generated from the comparator and outputting a fail count value; and a fail memory address generator generating a storage address for storing the fail signal when the comparator generates the fail signal.