发明名称 |
METHOD AND STRUCTURE FOR FINFET DEVICE |
摘要 |
The present disclosure provides a method for fabricating a fin-like field-effect transistor (FinFET). The method includes forming a first fin structures over a substrate, forming a patterned oxidation-hard-mask (OHM) over the substrate to expose the first fin structure in a first gate region of a n-type FET region, forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region, forming a second fin structure in a PFET region, forming dummy gates, forming source/drain (S/D) features, replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region and a second HK/MG in the PFET region. |
申请公布号 |
US2015303198(A1) |
申请公布日期 |
2015.10.22 |
申请号 |
US201414254072 |
申请日期 |
2014.04.16 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Ching Kuo-Cheng;Fung Ka-Hing;Chang Chih-Sheng;Wu Zhiqiang |
分类号 |
H01L27/092;H01L29/165;H01L29/161;H01L29/49;H01L21/311;H01L21/02;H01L21/8238;H01L29/66;H01L21/306;H01L29/16;H01L29/51 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
1. A method, comprising:
providing a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region; forming first fin structures in the NFET region and the PFET region; forming a patterned oxidation-hard-mask (OHM) over the NFET region and PFET region to expose the first fin structure in a first gate region of the NFET region; forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region; forming a second fin structure in the PFET region after covering the NFET with a hard mask layer; forming dummy gates in the first gate region and a second gate region in the second fin structure; forming a first source/drain (S/D) features in a first S/D region in the first fin structure in the NFET region; forming a second S/D feature in a second S/D region in the second fin structure in the PFET region; replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region, including wrapping over an upper portion of the first fin structure in the first gate region; and replacing the dummy gates by a second HK/MG in the PFET region, including wrapping over an upper portion of the second fin structure in the second gate region. |
地址 |
Hsin-Chu TW |