发明名称 LAMINATED SEMICONDUCTOR DEVICE AND CONNECTION METHOD
摘要 <p>PROBLEM TO BE SOLVED: To provide a laminated semiconductor device capable of preventing performance degradation due to a power drop by devising arrangement of power supply wiring or by any other means.SOLUTION: The laminated semiconductor device includes a main chip 10 and a sub chip 20 placed on the main chip 10. The sub chip 20 includes a power circuit which has an impedance lower than that of a first circuit mounted on the main chip and which has a power supply IO30 and a wiring intersection section 41 by a power supply wiring 40, and further a TSV for electrically connecting the first circuit with the wiring intersection section 41.</p>
申请公布号 JP2015185723(A) 申请公布日期 2015.10.22
申请号 JP20140061545 申请日期 2014.03.25
申请人 MITSUBISHI ELECTRIC CORP 发明人 NAEZAKI HIROHIDE
分类号 H01L25/065;H01L25/07;H01L25/18 主分类号 H01L25/065
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