LINEAR SAMPLER

摘要

A frequency conversion circuit having a plurality of N signal channels, each signal channel includes a column III-V semiconductor sampler coupled the input signal and being responsive to sampling signals and a column IV semiconductor controllable time delay for producing the train of sampling signals in response to a train of pulses produced on the column IV semiconductor, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay and wherein each one of the sampling signals is produced by the time delay in each one of the channels with a period T and a duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains.