Scheduling in a multicore architecture

摘要

This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

主权项

1. A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the method comprising:
providing a first configuration queue of executable transactions corresponding to a first configuration of the reconfigurable logic and a second configuration queue of executable transactions corresponding to a second configuration of the reconfigurable logic, the reconfigurable logic comprising one of a field programmable gate array (FPGA) or a memory, the executable transactions allocated to and ready for execution by the reconfigurable logic; providing a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions; linking the executable transaction schedulers together into a multilevel scheduler; outputting the most eligible executable transaction from the multilevel scheduler to one of the first configuration queue and the second configuration queue; outputting the executable transactions of the first configuration queue to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; reconfiguring the reconfigurable logic according to a second configuration when a pre-determined threshold is reached; and outputting the executable transactions of the second configuration queue to the configurable processor element for execution when the reconfigurable logic is configured according to the second configuration.