System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator

摘要

Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.

主权项

1. An apparatus comprising:
receiver logic, coupled to a first agent, the receiver logic to comprise: a phase interpolator to receive a reference clock and to generate a phase interpolator clock; Digital Eye Width Monitor (DEWM) logic, at least a portion of which is in hardware, to receive the reference clock and the phase interpolator clock, the DEWM logic to measure a data eye width and to cause a reduction in an offset of the phase interpolator clock relative to a real data eye center, wherein the DEWM logic is to cause a reduction in the offset of the phase interpolator clock at least partially based on comparison of two determined offset values at two sides of a center of the measured data eye width.