Signal level detect circuit with reduced loss-of-signal assertion delay

摘要

A signal level detect circuit configured to assess an input signal with varying amplitude signal levels and to generate an indicator signal includes an input circuit configured to receive the input signal and to process the input signal, the input circuit including a first node on which the input signal is sampled; a comparator configured to compare the processed input signal to a signal level threshold and generate a comparator output signal; and an active discharge circuit configured to provide a first discharge current to the first node in response to the comparator output signal. The comparator output signal changes from a low output state to a high output state in response to the comparator input signal, and the active discharge circuit generates the first discharge current to discharge the sampled input signal on the first node after the comparator output signal changes to the high output state.

主权项

1. A signal level detect circuit configured to assess an input signal with varying amplitude signal levels on an input terminal and to generate an indicator signal indicative of the presence and absence of a valid signal at the input terminal, the signal level detect circuit comprising:
an input circuit configured to receive the input signal and to process the input signal, the input circuit comprising a first node on which the input signal is sampled; a comparator configured to receive the sampled input signal as a comparator input signal and to compare the sampled input signal to a signal level threshold where an amplitude level of the comparator input signal being above the signal level threshold is indicative of the valid signal and the amplitude level of the comparator input signal being below the signal level threshold is indicative of an invalid signal, the comparator generating a comparator output signal, wherein the valid signal is a data signal having a logical low state and a logical high state, and the invalid signal is not a data signal and does not have a logical low or logical high state; an output circuit configured to receive the comparator output signal and to generate the indicator signal having a first logical level indicating the presence of the valid signal at the input terminal and having a second logical level indicating the absence of the valid signal at the input terminal; and an active discharge circuit configured to provide a first discharge current to the first node in response to the comparator output signal, wherein the comparator output signal changes from a low output state to a high output state in response to the comparator input signal having an amplitude level above the signal level threshold, and the active discharge circuit generates the first discharge current to discharge the sampled input signal on the first node in response to the comparator output signal changing to the high output state indicating the detection of the presence of the valid signal at the input terminal.