配线图案之制造方法及电晶体之制造方法;MANUFACTURING METHOD OF WIRING PATTERN AND MANUFACTURING METHOD OF TRANSISTOR

摘要

本发明之配线图案之制造方法具有以下步骤：于基板上形成镀敷基底膜之前驱物膜，该前驱物膜含有具有由光反应性之保护基保护之胺基之第1形成材料；于上述前驱物膜之表面形成由光阻材料构成之光阻层；利用所欲之图案光对上述光阻层进行曝光；利用所欲之图案光对上述前驱物膜进行曝光而形成上述镀敷基底膜；使经曝光之上述光阻层显影并且将去保护后之保护基去除；及使无电镀敷用触媒析出于露出之上述镀敷基底膜之表面。; forming a photoresist layer made of a photoresist material on a front surface of the precursor film; exposing the photoresist layer with a desired pattern light; forming the plating undercoating film to expose the precursor film with a desired pattern light; developing the exposed photoresist layer and removing a deprotected protective group; and causing a non-electrolytic plating catalyzer to separate on a front surface of the exposed plating undercoating film.