Incremental Functional Verification of a Circuit Design

摘要

A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module.

主权项

1. A method for incrementally verifying a circuit design, the method comprising:
(a) representing a first subset of modules in the circuit design by one or more interpretive computer programming modules, wherein the circuit design is used to manufacture integrated circuits; (b) representing a second subset of modules in the circuit design by one or more hardware descriptive language (HDL) modules; (c) performing simulation of a mixed design which represents the first subset of the circuit design by the one or more interpretive computer programming modules and represents the second subset of the circuit design by the one or more HDL modules; (d) translating a part of the first subset of modules into a HDL module to include the translated part in the second subset of modules and remove the translated part from the first subset of modules, responsive to the simulation of the mixed design being successful; and (e) repeating (a) through (d) at least once.