PROCESSING FIXED AND VARIABLE LENGTH NUMBERS

摘要

Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

主权项

1. A processor, comprising:
a floating point unit; a logic circuit coupled to the floating point unit, wherein the logic circuit is configured to:
receive an operation, a first operand and a second operand, wherein each of the first operand and the second operand include a sign and exponent block, a length block, and one or more mantissa digits;perform the received operation on the first operand and the second operand to generate a first result, wherein the first result includes a sign and exponent block, a length block, and one or more mantissa digits;process each of the first operand and the second operand responsive to a determination that the first operand and the second operand are fixed-length numbers; andperform, responsive to the determination that the first operand and the second operand are fixed-length numbers, the received operation on the processed first operand and the processed second operand to generate a second result, wherein the second result includes a sign and exponent block, and one or more mantissa digits.