| 摘要 |
<p>Plural unit delay circuits (10A, 10B) connected in series and an output circuit (20) that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit (10A) includes a selector (12A) that outputs a signal input to a second input terminal (DIN2A) when the set signal is "0", and outputs a signal input to a first input terminal (DIN1A) when the set signal is "1", and an inverter (11A) that inverts and outputs an output of the selector from a second output terminal (DOUT2A). A second unit delay circuit (10B) includes an inverter (11B) that inverts the signal input to the first input terminal (DIN1B) and outputs from a first output terminal (DOUT1B), and a selector (12B) that outputs the signal input to the second input terminal (DIN2B) when the set signal is "0", and outputs an output of the inverter when the set signal is "1" from the second output terminal (DOUT2B).</p> |
