发明名称 インタフェース装置、およびメモリバスシステム
摘要 An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.
申请公布号 JP5793690(B2) 申请公布日期 2015.10.14
申请号 JP20140531021 申请日期 2013.11.19
申请人 パナソニックIPマネジメント株式会社 发明人 石井 友規;山口 孝雄;吉田 篤;得津 覚;曽我 祐紀
分类号 G06F12/00;G06F13/16 主分类号 G06F12/00
代理机构 代理人
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