发明名称 Dynamic deterministic address translation for shuffled memory spaces
摘要 A memory storage scheme specially adapted for wear leveling (or other reorganization of logical memory space). Memory space includes a logical memory space of M addressable blocks of data, stored as rows or pages, and N substitute rows or pages. Data is periodically shuffled by copying data from one of the M addressable blocks to a substitute row, with the donating row then becoming part of substitute memory space, available for ensuing wear leveling operations, using a stride address. The disclosed techniques enable equation-based address translation, obviating need for an address translation table. An embodiment performs address translation entirely in hardware, for example, integrated with a memory device to perform wear leveling or data scrambling, in a manner entirely transparent to a memory controller. In addition, the stride address can represent an offset greater than one (e.g., greater than one row) and can be dynamically varied.
申请公布号 US9158672(B1) 申请公布日期 2015.10.13
申请号 US201213644550 申请日期 2012.10.04
申请人 Rambus Inc. 发明人 Zheng Hongzhong;Haukness Brent Steven
分类号 G06F12/00;G06F12/02 主分类号 G06F12/00
代理机构 代理人 Schuyler Marc P.
主权项 1. A method of managing memory, the method comprising: mapping a set of M logically addressable blocks of data in a one-to-one correspondence to a first set of M physically addressable storage sections in the memory; tracking a second set of N physically addressable storage sections in the memory, where N≧1, the second set not overlapping the first set; maintaining a stride value S, where S>1; exchanging a storage section of the first set with a storage section in the second set, where the storage section of the first set that is exchanged is selected based on a distance equal to the stride value S in logical address space from one of the M logically addressable blocks of data that was stored in a storage section the subject of an immediately previous exchange; and repeating the exchanging for different storage sections of the first set; where the method further comprises tracking a third set of physically addressable storage sections in the memory, the third set not overlapping the first set or the second set, and after a selected number C of the exchanges, increasing the number of storage sections in one of the first set or the second set by removing sections from the third set and adding the removed sections to the first set or the second set.
地址 Sunnyvale CA US