Non-binary decoder architecture and control signal logic for reduced circuit complexity

摘要

A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log2X inputs for receiving the clock signal inputs.

主权项

1. A method of decoding, comprising:
providing an array including a plurality of lines of addressable elements; providing a decoder for sequentially enabling the lines of the array responsive to a plurality of clock signal inputs; and providing the plurality of clock signal inputs to the decoder to sequentially enable outputs of the decoder, wherein one or more of the clock signal inputs has a non-binary duty cycle.