Systems and methods for mitigating print-out defects

摘要

The present disclosure provides methods and systems for mitigating print-out defects that result during semiconductor simulation and/or fabrication. One of the methods disclosed herein includes steps of receiving a first desired sub-layout and a second desired sub-layout and of optimizing the first desired sub-layout and the second desired sub-layout to generate a first optimized sub-layout and a second optimized sub-layout. The method further includes simulating the first optimized sub-layout and the second optimized sub-layout and of identifying one or more print-out defects in the simulated first optimized sub-layout and the simulated second optimized sub-layout. By comparing the simulated first optimized sub-layout and the simulated second optimized sub-layout it may be determined whether or not print-out defects in the simulated second optimized sub-layout are covered by the first desired sub-layout such that the first optimized sub-layout may be used to pattern material layers.

主权项

1. A method for mitigating defects during a semiconductor fabrication process, the method comprising:
receiving a first desired sub-layout and a second desired sub-layout; optimizing the first desired sub-layout and the second desired sub-layout to generate a first optimized sub-layout and a second optimized sub-layout; simulating the first optimized sub-layout and the second optimized sub-layout; identifying one or more print-out defects in the simulated first optimized sub-layout and the simulated second optimized sub-layout; comparing the simulated first optimized sub-layout and the simulated second optimized sub-layout to determine whether print-out defects in the simulated second optimized sub-layout fall within geometries defined by features in the first desired sub-layout; when the print-out defects in the simulated second optimized sub-layout fall within geometries defined by features in the first desired sub-layout, indicating that the second optimized sub-layout is allowable; and implementing the second optimized sub-layout as a mask for semiconductor fabrication.