Flash interface error injector

摘要

A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.

主权项

1. A processor-implemented method of error injection at a flash interface of a flash-based array, the method comprising:
executing, using a processor, bit flip probability logic configured to identify one or more bits to be flipped; and executing, using the processor, a plurality of error injection logic blocks, each of the plurality of error injection logic blocks corresponding with a respective flash channel of the flash-based array, to inject errors at the one or more bits defined by the bit flip probability logic.