| 主权项 |
1. A digital controlled oscillator, comprising:
a ring delay circuit which includes delay elements connected in ring shape, the number of the delay elements being m (m is an integer of 2 or more), and which transmits a pulse signal with delay; a timing signal generation section which generates a timing signal corresponding to timing selection data from passing signals outputted from the delay elements, in accordance with the timing selection data specifying any of timings which are obtained by dividing a circulation period of the pulse signal in the ring delay circuit by m×n (n is an integer of 2 or more); and an output signal generation section which sets the timing selection data based on control data specifying a period of an output pulse signal and the timing selection data every time when the output pulse signal is outputted, and generates the output pulse signal in accordance with the timing selection data by using the timing signal outputted from the timing signal generation section, wherein the timing signal generation section generates the timings obtained by dividing the circulation period by m×n by using at least one pulse edge shift circuit which generates shift signals, the number of which is n, and whose timings differ from each other by a unit delay time from one input signal, the unit delay time being 1/n of delay time in the delay element. |
