发明名称 MULTI-LEVEL POWER CONVERTER
摘要 This is a multi-level converter comprising one or more arms (B) to each be connected between a voltage source (VDC) and a current source (I). Each arm comprises two stages (E1, E2) in cascade, the first to be connected to the voltage source (VDC), the second to be connected to the current source (I). The first stage (Et1) comprises several elementary stages (E1n, . . . , E12, E11) of rank one to n in cascade, the elementary stage (E11) of rank one being connected to the second stage (Et2) and the elementary stage (E1n) of rank n having to be connected to the voltage source (VDC). Each elementary stage (E1n) comprises a pair of identical cells of NPC type (Cen1, Cen2) in series, the connection being direct in the elementary stage of rank 1, the connection being made via n−1 capacitive cells ((Can(1), . . . Can(n−1)) for each elementary stage of rank greater than one, the second stage (Et2) comprising a floating capacitor cell (Ce10).
申请公布号 US2015288284(A1) 申请公布日期 2015.10.08
申请号 US201514635337 申请日期 2015.03.02
申请人 Schneider Toshiba Inverter Europe SAS 发明人 LAVIEVILLE Jean-Paul
分类号 H02M3/158;H02M5/42 主分类号 H02M3/158
代理机构 代理人
主权项 1. Multi-level converter comprising one or more arms (B), configured to each be connected between a voltage source (VDC) and a current source (I), in which the or each arm comprises two stages (E1, E2) connected in cascade with a first stage (Et1) intended to be connected to the voltage source (VDC), a second stage (Et2) intended to be connected to the current source (I), in which the first stage (Et1) comprises n elementary stages (E11, . . . , E1n) of rank one to n (n greater than one) connected in cascade, the elementary stage (E11) of rank one being connected to the second stage (Et2) and the elementary stage (E1n) of rank n being intended to be connected to the voltage source (VDC), characterized in that each elementary stage (E11, E1n) comprises a pair of identical cells of NPC type (Ce11, Ce12; Cen1, Cen2) connected in series, the connection being direct in the elementary stage (E1) of rank 1, the connection being made via n−1 capacitive cells (Can(1), Can(n−1)) for each elementary stage of rank n (n greater than one), the second stage (Et2) comprising a cell of floating capacitor type (Ce10).
地址 Pacy sur Eure FR