DOUBLE PATTERNED STACKING TECHNIQUE

摘要

A double patterned CMOS device includes a first set of stacked transistors, a second set of stacked transistors, and a set of transistors. The first set of stacked transistors includes first and second transistors. The first transistor has a first transistor active region and the second transistor has a second transistor active region. The second set of stacked transistors is adjacent the first set of stacked transistors. The second set of stacked transistors includes third and fourth transistors. The third transistor has a third transistor active region and the fourth transistor has a fourth transistor active region. The set of transistors is adjacent the first set of stacked transistors. The set of transistors includes a fifth transistor. The fifth transistor has a fifth transistor active region. The first, second, third, and fourth transistor active regions satisfy certain distance relationships from each other.

主权项

1. A double patterned complementary metal oxide semiconductor (CMOS) device comprising:
a first set of stacked transistors comprising a first transistor and a second transistor, the first transistor having a first transistor active region and the second transistor having a second transistor active region; a second set of stacked transistors adjacent the first set of stacked transistors, the second set of stacked transistors comprising a third transistor and a fourth transistor, the third transistor having a third transistor active region and the fourth transistor having a fourth transistor active region; and a set of transistors adjacent the first set of stacked transistors, the set of transistors comprising a fifth transistor, the fifth transistor having a fifth transistor active region, wherein the first transistor active region is greater than or equal to a distance d from the second transistor active region, the third transistor active region is greater than or equal to the distance d from the fourth transistor active region, the distance d is a minimum distance based on a patterning process for the device, the first transistor active region is approximately greater than a distance 0.5d from the third transistor active region, the second transistor active region is approximately greater than the distance 0.5d from the fourth transistor active region, and the fifth transistor active region is approximately greater than the distance 0.5d from the first transistor active region and the second transistor active region.