| 发明名称 |
STRESS MITIGATION STRUCTURE FOR WAFER WARPAGE REDUCTION |
| 摘要 |
An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation. |
| 申请公布号 |
US2015287677(A1) |
申请公布日期 |
2015.10.08 |
| 申请号 |
US201414483944 |
申请日期 |
2014.09.11 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
LAN Je-Hsiung Jeffrey;BERDY David Francis;ZUO Chengjie;KIM Daeik Daniel;YUN Changhan Hobie;VELEZ Mario Francisco;MUDAKATTE Niranjan Sunil;MIKULKA Robert Paul;KIM Jonghae |
| 分类号 |
H01L23/522;H01L21/768;H01L23/528;H01L21/283 |
主分类号 |
H01L23/522 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit device comprising:
a substrate; a first conductive stack comprising a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate; and a second conductive stack comprising the BEOL conductive layer at a second elevation relative to the substrate that differs from the first elevation. |
| 地址 |
San Diego CA US |
