Prefetch address translation using prefetch buffer based on availability of address translation logic

摘要

Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.

主权项

1. A computer system for prefetch address translation, the system comprising:
a processor, the processor comprising:
address translation logic;a translation lookaside buffer (TLB);prefetch logic; anda prefetch buffer, the system configured to perform a method comprising:
issuing, by the prefetch logic, a prefetch request comprising a virtual page address;based on the prefetch request missing the TLB, determining whether the address translation logic is currently available to handle the prefetch request, wherein the address translation logic is not currently available to handle the prefetch request based on the address translation logic being busy performing a current translation request at the time of the issuing of the prefetch request; andbased on determining that the address translation logic of the processor is not currently available to handle the prefetch request:
comparing a virtual page address of the prefetch request to a virtual page address of the current translation request; andbased on the virtual page address of the prefetch request matching the virtual page address of the current translation request, storing the prefetch request in the prefetch buffer.