| 摘要 |
The present invention discloses use of quantum dot gate FETs as a nonvolatile memory element that can be used in flash memory architecture as well as in a nonvolatile random access memory (NVRAM) configuration that does not require refreshing of data as in dynamic random access memories. Another innovation is the design of quantum dot gate nonvolatile memory and 3-state devices using modulation doped field-effect transistors (MODFETs), particularly MOS-gate field effect transistors. The cladded quantum dot gate MODFETs can be designed in Si—SiGe, InGaAs—InP and other material systems. The incorporation of 3-state FET devices in static random access memory (SRAM) cell is described to result in advanced multi-state memory operation. Unlike conventional SRAMs, the 3-state QD-FET based of SRAMs provides 3 and 4-state memory operation due to the utilization of the intermediate states particularly in CMOS configuration. QD-gate FETs, potentially suitable for 8 nm channel lengths, in vertical configuration (VFET) are also described. |
| 主权项 |
1. A nonvolatile memory device, comprising:
a modulation doped field-effect transistor (MODFET) structure having a source, a drain, a gate region and a semiconductor substrate in which a transport channel is formed between the source and the drain, wherein the transport channel is controlled by a voltage applied to the gate region, wherein the gate region includes a multilayer structure having: a first layer located proximate to the transport channel, wherein the transport channel is constructed from at least one material selected from the group consisting of an insulator and a wide energy gap lattice matched semiconductor and a pseudomorphic semiconductor layer, wherein the first layer serves as a spacer layer, a second layer located proximate to the first layer, wherein the second layer is constructed from a doped semiconductor material having donor impurities that provide electrons as a supply layer to the transport channel, a third layer located proximate to the second layer wherein the third layer includes a semiconductor layer having acceptor type impurities, and a first set of cladded quantum dots assembled on the third layer, wherein the first set of cladded quantum dots is selected from a group consisting of SiOx-cladded Si nanocrystal quantum dots and GeOx-cladded Ge nanocrystal quantum dots, wherein the first set of cladded quantum dots include at least one cladded nanocrystal layers, a first insulator layer deposited over the first set of cladded quantum dots, wherein the first insulator layer is deposited with a fourth layer to facilitate deposition of cladded quantum dots, wherein the fourth layer is deposited with a second insulator layer, a second set of cladded quantum dots having at least one cladded nanocrystal layers deposited over the second insulator layer, a third insulator layer deposited over the second set of cladded quantum dots, and the first and second set of cladded quantum dots configured to form a floating quantum dot gate and a control gate electrode over the third insulator layer. |
