发明名称 SERIAL MULTIPLY ACCUMULATOR FOR GALOIS FIELD
摘要 A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.
申请公布号 US2015277857(A1) 申请公布日期 2015.10.01
申请号 US201414228763 申请日期 2014.03.28
申请人 Storart Technology Co., Ltd. 发明人 HUNG Jui Hui;YEN Chih Nan
分类号 G06F7/72 主分类号 G06F7/72
代理机构 代理人
主权项 1. A serial multiply accumulator for operation of two multiplications and one addition over Galois field, comprising: a first element feeding circuit for sequentially outputting first elements in the Galois field per clock cycle; a second element feeding circuit for sequentially outputting second elements in the Galois field per clock cycle; a plurality of first calculating circuits, linked successively from upstream to downstream, each receiving the first element, the second element, one third element, and one fourth element per clock cycle, receiving an operating data from an upstream-linked first calculating circuit, optionally receiving a feedback data, producing two products by multiplying the first element by the third element and multiplying the second element by the fourth element, and outputting another operating data downstream, the outputted operating data being available from adding one product to the other, adding the products to the received operating data, adding the products to the feedback data, or adding the products and the received operating data to the feedback data, wherein the first calculating circuit arranged most upstream doesn't receive the operating data from other first calculating circuit; and a second calculating circuit, linked to the first calculating circuit arranged the most downstream, for receiving the first element, the second element, one third element, and one fourth element per clock cycle, receiving the outputted operating data from the linked first calculating circuit, producing two products by multiplying the first element by the third element and multiplying the second element by the fourth element, and outputting the feedback data, the outputted operating data being available from adding one product to the other or adding the products to the received operating data; wherein the first elements, the second elements, the third elements and the fourth elements have the same amount, the third element provided to one of the first calculating circuit or the second calculating circuit is different from that provided to other first calculating circuits, and the fourth element provided to one of the first calculating circuit or the second calculating circuit is different from that provided to other first calculating circuits.
地址 Hsinchu TW