EDGE-TRIGGERED PULSE LATCH

摘要

A pulse latch is provided that latches a ground signal responsive to decoded signal carried on a decoded signal node. The pulse latch includes a reset logic circuit that controls a switch coupled between the decoded signal node and ground such that when the switch is turned on by the reset logic circuit, the decoded signal node is grounded. The reset of the decoded signal node by the reset logic circuit is responsive to a ground signal. The ground signal is generated so as to be responsive to a clock edge. Thus, the reset of the decoded signal node is also responsive to the clock edge.

主权项

1. A pulse latch, comprising:
a decoding circuit configured to decode address signals to determine whether a decoded signal carried on a decoded signal node is asserted or de-asserted in a current cycle of a memory clock; a ground signal generator configured to generate a ground signal such that the ground signal is de-asserted in response to a first edge of the memory clock and asserted in response to a second edge of the memory clock; a first switch operable to couple the ground signal to a latch responsive to the decoded signal being asserted; a second switch coupled between the decoded signal node and ground; and a reset logic circuit configured to control the second switch to close responsive to both the ground signal and the decoded signal being de-asserted and to control the second switch to open responsive to the ground signal and/or the decoded signal being asserted.