发明名称 |
Register Transfer Level (RTL) Test Point Insertion Method to Reduce Delay Test Volume |
摘要 |
A method includes inserting test points into a circuit for reducing the number of specified bits required for transition fault testing of the circuit by reducing the dependency of a second time-frame pattern of the circuit on a first time-frame pattern of the circuit. Preferably, inserting the test points includes controlling directly scan flip-flops of the circuit in the second time-frame requiring a number of scan flip-flops to be specified in the first time-frame for reducing the number of specified bits to detect transition faults.
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申请公布号 |
US2008092093(A1) |
申请公布日期 |
2008.04.17 |
申请号 |
US20070858216 |
申请日期 |
2007.09.20 |
申请人 |
NEC LABORATORIES AMERICA, INC. |
发明人 |
BALAKRISHNAN KEDARNATH;FANG LEI |
分类号 |
G01R31/3185 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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