发明名称 Partial Enhanced Scan Method for Reducing Volume of Delay Test Patterns
摘要 A method includes selecting at least one regular scan cell that is replaced with a corresponding one of an enhanced scan cell in a scan chain for scan based delay testing of the digital circuit, controlling the enhanced scan cell with a skewed load approach, and controlling regular scan cells of the scan chain with a broadside approach. More specifically, this reduces test sequence lengths and achieves higher delay fault coverage, without having to pay high cost to drive all scan cells by the skewed load approach, which requires a faster switching than the broadside approach. No additional pins are required for driving enhanced scan cells because the drive signal for switching the enhanced scan cells is derived from the signal for driving the regular scan cells.
申请公布号 US2008091998(A1) 申请公布日期 2008.04.17
申请号 US20070851137 申请日期 2007.09.06
申请人 NEC LABORATORIES AMERICA, INC. 发明人 WANG SEONGMOON
分类号 G01R31/3183 主分类号 G01R31/3183
代理机构 代理人
主权项
地址