| 摘要 |
An application-specific integrated circuit for use in optimizing a packet network including a processing unit that processes defined sequences of assembler language and executes defined sequences of assembler instructions; program and data memory that stores the defined sequences of assembler instructions; an internal data bus; and an input/output (I/O) interface arranged between the internal data bus and at least one external network device for communicating data packets containing network performance information between the internal data bus and the at least one external network device.
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