A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command.
申请公布号
WO2007106481(A1)
申请公布日期
2007.09.20
申请号
WO2007US06300
申请日期
2007.03.13
申请人
MICRON TECHNOLOGY, INC.;DE SANTIS, LUCA;PILOLLI, LUIGI