发明名称 INSPECTION METHOD AND DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress the increase of the area of the semiconductor integrated circuit at a minimum by largely simplifying a comparator when using BIST technology at inspection, and to eliminate change operation in an inspection facility outside the semiconductor integrated circuit, with the changes in an objective circuit to be inspected. SOLUTION: Even when an additional bit string 321 is incorporated into an inspection response bit string 312 outputted by the objective circuit 310 and a first inspection response bit string 310 is changed with changes in the circuit 310, properly selecting the additional bit string 321 enables keeping the expected value 341 of a compression signature at a fixed value. Thus, the configuration of an acceptance determination section 340 including the expected value comparison circuit can be simplified, to suppress the increase of the area. When the expected value comparison is performed at the outside of the semiconductor integrated circuit, changes in an inspection program becomes unnecessary, since the expected value is invariable. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007240390(A) 申请公布日期 2007.09.20
申请号 JP20060064978 申请日期 2006.03.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ATOI YOSHIYUKI
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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