发明名称 |
SERIAL COMMUNICATION INTERFACE WITH LOW CLOCK SKEW |
摘要 |
A communication interface for use in an integrated circuit comprises a clock root circuit (110) configured to receive the clock reference signal and to generate a clock tree signal. A first lane circuit (220b) is coupled to the clock root circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a first interface circuit. A second lane circuit (220a) is coupled to the first lane circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a second interface circuit. In one embodiment, each lane circuit includes a buffer (222) configured to receive the clock tree signal and a multiplexer (228) configured to selectively deliver the clock tree signal to the interface circuit. Advantages of the invention include a modular construction of a communication interface having low clock skew. |
申请公布号 |
WO2007042997(A2) |
申请公布日期 |
2007.04.19 |
申请号 |
WO2006IB53698 |
申请日期 |
2006.10.09 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;U.S. PHILIPS CORPORATION;JOORDENS, GEERTJAN |
发明人 |
JOORDENS, GEERTJAN |
分类号 |
G06F1/10;G06F13/38 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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