发明名称 |
Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning |
摘要 |
By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.
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申请公布号 |
US2006223250(A1) |
申请公布日期 |
2006.10.05 |
申请号 |
US20050280484 |
申请日期 |
2005.11.16 |
申请人 |
ROMERO KARLA;KAMMLER THORSTEN;LUNING SCOTT;VAN MEER HANS |
发明人 |
ROMERO KARLA;KAMMLER THORSTEN;LUNING SCOTT;VAN MEER HANS |
分类号 |
H01L21/302;H01L21/31;H01L21/8234 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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