| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which a required amount of wiring is reduced, a wiring delay is restrained, and a man-hour required for modification work can be reduced when the semiconductor integrated circuit is modified in design. SOLUTION: When a layout is designed, an inverter composed of NOR gates 127, 129 and NOR gates 128, 130 with short-circuited input terminals is arranged as a delay time adjustment buffer. When a logic module 1 is modified in design when the layout is designed, for instance, the NAND gate 130 is used as an ECO cell for carrying out modification in wiring. Additional wiring 306 of a short length is capable of coping with a requirement in the module 1, and return wiring can be dispensed with because the NAND gate 130 is located on a signal transmission route. As an additional amount of wiring can be reduced, the amount of the delay adjusting work is reduced. Moreover, a wiring space retained between the logic modules 1 can be reduced. COPYRIGHT: (C)2007,JPO&INPIT
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