| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method for correcting received sample clock timing by which proper correction of the received sample clock timing can be executed by accurately measuring an error between the received sample clock timing and ideal received sample clock timing, and to provide a digital signal receiver. <P>SOLUTION: An A/D converter 2 executes digital conversion to an in-phase signal (an I signal) and an orthogonal signal (a Q signal) output from an orthogonal detector 1. A sample clock timing error measuring part 4 calculates the error direction and the error amount of a sample point by comparing the received IQ signals when ideally receiving known transmission preamble data with the IQ signals output by the A/D converter 2, and sets a phase correction value for correcting the calculated error to a phase shifter 5. The phase shifter 5 corrects timing of a clock from a clock generator on the basis of the phase correction value. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
