发明名称 |
Sharing idled processor execution resources |
摘要 |
A processor including a plurality of logical processors, and an instruction set, the instruction set including of one or more instructions which when executed by a first logical processor, cause the first logical processor to make a processor execution resource previously reserved for the first processor available to a second processor in the plurality of processors in response to the first logical processor being scheduled to enter an idle state.
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申请公布号 |
US2005172292(A1) |
申请公布日期 |
2005.08.04 |
申请号 |
US20040772750 |
申请日期 |
2004.02.04 |
申请人 |
YAMADA KOICHI;KAY ALLEN M. |
发明人 |
YAMADA KOICHI;KAY ALLEN M. |
分类号 |
G06F9/30;G06F9/38;G06F9/46;G06F9/50;(IPC1-7):G06F9/46 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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